1. Field of the Invention
The invention relates to a method for forming a low dielectric constant layer, and more particularly to a method for forming a low dielectric constant layer and treating the low dielectric constant layer in a semiconductor device.
2. Description of the Prior Art
It is the nature of semiconductor physics that as the feature sizes are scaled down, the performance of internal devices in integrated circuits improves in a compounded fashion. That is, the device speed as well as the functional capability improves. The overall circuit speed, however, becomes more dependent upon the propagation speed of the signals along the interconnects that connect the various devices together. With the advent of very and ultra large scale integration (VLSI and ULSI) circuits, it has therefore become even more important that the metal conductors that form the interconnections between devices as well as between circuits in a semiconductor have low resistivities for high signal propagation. Copper is often preferred for its low resistivity to electromigration and stress voiding properties.
On the other hand, considerable attention has focused on the replacement of silicon dioxide with new materials, particular material having lower dielectric constants, since both capacitive delays and power consumption depend on the dielectric constant of the insulator. Accordingly, circuit performance enhancement has been sought by combining the copper conductors with low dielectric constant insulators (k less than approximately 4).
An example of a single damascene process using a low k dielectric material is depicted in FIG. 1. A low k dielectric material 142 such as benzocyclobutene (BCB) or the material known as FLARE (manufactured by Allied Signal) is spun on an interconnect layer 140. A cap layer 144 is deposited on the low k dielectric layer 142. An another example of a dual damascene process sequence using a low k dielectric, having trenches with underlying via holes that are etched in the low k dielectric material before metal deposition and chemical-mechanical polishing, is deposited in FIG. 2. This commonly used method of forming the trenches together with the via holes employs etch stop layers and photoresist masks. A bottom stop layer 114 is deposited over an existing interconnect pattern formed in an interconnect layer 110. A layer of low k dielectric material 116 is then deposited on the bottom stop layer 114. A via 128 is formed within this low k dielectric layer 116. On the other hand, a trench 126 is formed within a second layer 122 of low k dielectric material spun coated on a middle stop layer 118.
However, these spin-on materials of low k dielectric usually have carbon double or triple bonds compounds used for forming cross-linking during curing step. Such these low k materials may have low mechanical strength, poor dimensional stability, poor temperature stability, high moisture absorption and permeation, and so on. To be specific, because of high moisture absorption, those unexhausted unsaturated bonds in curing step are susceptible to moisture to form carboxyl compound with higher k dielectric constant.
It is an object of the present invention to provide a method for low k material treatment. The unsaturated carbon bonds of low k material unexhausted in curing step are saturated for maintaining low dielectric constant.
It is another object of the present invention to provide a method for forming dielectric layer of low dielectric constant. The low k material is treated with hydrogen for saturation of unexhausted unsaturated carbon bonds.
In the present invention, a method for forming low dielectric constant layer in a semiconductor device comprises providing the semiconductor device. A dielectric layer is formed on the semiconductor device, which has a constituent of a plurality of unsaturated carbon bonds compounds. The dielectric layer is then treated with hydrogen.